Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. In chip packages having two or more dies arranged across an interposer of the chip package, routing between outputs on facing sides of the dies becomes complicated, often requiring complex interconnect schemes with the interposer. Such complex interconnect schemes may undesirably rob device performance. Additionally, dies arranged across the interposer usually require unique designs in order to have specific alignment between chip I/O's. As each unique design requires a separate maskset and tapeout, the fabrication costs needed to produce multiple individual dies for a single package assembly can often be undesirably high.
Therefore, a need exists for an improved integrated circuit (IC) die that addresses one or more of the problems set forth above.